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AD421
–3–
REV. C
TIMING CHARACTERISTICS
1, 2, 3
Parameter
(B Versions)
Units
Conditions/Comments
t
CK
t
CL
t
CH
t
DW
t
DS
t
DH
t
LD
t
LL
t
LH
100
50
50
30
30
0
50
50
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
NOTES
1
Guaranteed by characterization at initial product release, not production tested.
2
See Figures 1 and 2.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of (V
IN
+ V
IL
)/2; tr and tf should not exceed 1
μ
s on any digital
input.
Specifications subject to change without notice.
WORD "N"
WORD "N +1"
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
CLOCK
DATA
LATCH
B
(
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(
Figure 1. Serial Interface Waveforms (Normal Data Load)
CLOCK
DATA
LATCH
t
CK
t
CL
t
CH
t
DS
t
DH
t
DW
t
LD
t
LL
t
LH
Figure 2. Serial Interface Timing Diagram
(V
CC
= +3 V to +5 V, T
A
= T
MIN
to T
MAX
unless otherwise noted)
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